1. Field of the Invention
The present invention relates to structures for memory devices and particularly to high density memory cell device structures.
2. Description of Related Art
Memory devices utilize memory cells arranged in an array to store data. Operations are performed on specific memory cells in the array of memory cells through the use of decoders which connect to the word lines and bit lines in the array, supported by other peripheral circuits located in a peripheral region on the memory device. In typical memory device structures, the decoders are disposed adjacent to the array of memory cells increasing the area of the device. Additionally, other peripheral circuits are disposed in peripheral regions around the decoders and the array of memory cells increasing the area of the device. This structure is utilized in various types of memory, including volatile DRAM memory and non-volatile NOR/NAND Flash memory.
This memory device structure is disadvantageous for numerous reasons. First, the memory device structure with the decoders and the peripheral region in which the peripheral circuits are disposed being around the array of memory cells has a large footprint. The large footprint of the memory device structure results in large chip sizes.
Second, this memory device structure is disadvantageous for the high costs of manufacturing. Often the manufacturing steps needed to form the memory array are different than those needed to form the decoders and peripheral circuits. This requires complex interleaving of the processes.
It is therefore desirable to provide a memory device structure with a small footprint. It is also desirable to provide a memory device structure that can be manufactured at lower costs.